ASIC Design Verification Junior Staff Engineer

June 16, 2020
PHOENIX, ‎Arizona
Job Type


Accenture is a leading global professional services company, providing a broad range of services and solutions in strategy, consulting, digital, technology and operations. Combining unmatched experience and specialized skills across more than 40 industries and all business functions – underpinned by the world’s largest delivery network – Accenture works at the intersection of business and technology to help clients improve their performance and create sustainable value for their stakeholders. With approximately 469,000 people serving clients in more than 120 countries, Accenture drives innovation to improve the way the world works and lives.

People in our Client Delivery & Operations career track drive delivery and capability excellence through the design, development and/or delivery of a solution, service, capability or offering. They grow into delivery-focused roles, and can progress within their current role, laterally or upward.

Job Description:

We are looking for SoC Design Verification Engineer to provide design verification services for multi CPU/DSP SoC.

  • Testbench development - System Verilog UVM and C tests
  • Integration/development of C tests/APIs and SW build flow
  • Integration/development of UVM mailboxes and HW/SW communication components
  • Integration of lower level UVM testbenches
  • Test plan development
  • Power Aware testbench development and simulations
  • Seamless porting between simulation/emulation/prototyping platforms
  • Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto
  • Coverage collection and closure
  • Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope


Basic Qualifications:

  • 1-3 years of experience in RTL Design and Verification area of which
  • 1+ years of experience in SoC Design Verification and HW/SW verification
  •  1+ years within any of the following:
    • System Verilog UVM and vertical tetsbench integration
    • Low level HW/SW interaction and debug
    • Multi CPU and debug architectures
    • Development of fully automated flows

Preferred Qualification: 

  • Experience with low level SW debug - disasm, Tarmac, trace
  • Experience with coresight architecture
  • Experience with embedded SW low level concepts and debug - Tarmac, ROM, RAM, linkers, elf, disasm, code sections, cache, security
  • Experience with coverage merging across simulation and emulation
  • Experience with Power Aware and Gate Level Netlist in Emulation
  • Experience with development of fully automated flows
  • Experience with Gate Level Simulations
  • Python Scripting

Applicants for employment in the US must have work authorization that does not now or in the future require sponsorship of a visa for employment authorization in the United States and with Accenture.

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