Senior ASIC DV Engineer

Job Description:

You will contribute to the development of complex SOCs targeted towards Touch Controllers/Wireless Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include:

• Architect block and full-chip verification environments using HVLs and constrained random techniques (UVM) for SOCs with embedded CPUs and mixed signal interfaces.
• Develop test plans and coverage metrics from specifications and write block and chip-level tests.
• Debug RTL and Gate simulations and work with design engineers to verify fixes.
• Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC.
• Replicate silicon bugs in simulation environment and validate fixes or SW workarounds.
• Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup.
• Evaluate latest verification methodologies and develop scripts etc. to automate verification flows.
• Knowledge of C, Low Power Verification (UPF) and Mixed-signal simulations (AMS, Spice) etc.
• Assist in the development of embedded FW.

MS / PhD is preferred.  12+ years experience.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Apply Here