Sr. Staff, Digital SoC Engineer

Renesas is looking for Digital IC Design Engineering candidates for a position in Austin, TX. This position will be responsible for architecting our next generation Digital Multi-phase power ASIC products. Designs include embedded MCUs, volatile and non-volatile memory, high speed signal processing data paths, on-chip A/D and D/A converters, and industry standard serial bus interfaces. System level applications include regulated PWM DC-to-DC power converters, system power monitoring, and board level telemetry functions. This leadership position requires the development of differentiable advances in cost, power, performance, security and usability of our IC’s through SoC architecture.  This may involve: MCU, peripheral IP, and memory IP selection, partitioning of hardware/firmware to benefit cost/power/flexibility, maximizing applications covered with a given design through NVM or firmware configuration, simplifying the user experience through elegant memory space management, conceiving of controllability and observability points meaningful to the end user and facilitating through hardware/firmware/memory.

Primary Responsibilities:

• Own SoC architecture definition
  • quantifying trade-offs in, and partitioning functions among, analog and digital hardware and firmware
  • IP selection: MCU and peripherals, memory, IO
• Support business planning including: schedule, resource allocation, development cost and product unit cost
• Hands on execution of RTL in Verilog for use in a Mixed Signal Integrated Circuit
• Oversee design specifications, IC verification and validation plans
• Collaborate within a highly experienced team with extensive cross-functional engineering skills
• Contribute to Industry Standards related to the Voltage Regulator market space
• Conduct design, architecture, and verification reviews
• Signoff responsibility for verification coverage and spec compliance
• Continual improvements in development cycle times and product quality through staff training and process improvements
• Mentor and train junior engineers

Qualifications:

• Master’s degree or higher in Electrical Engineering with a minimum of 8 years of relevant industry experience
• Experience with architecting digital designs and writing device-level or sub-system specifications
• Experience with Verilog and/or SystemVerilog for digital design and verification
• Experience creating block and chip-level verification tests and verification plan development
• Excellent oral and written communications skills

Preferred Skills/Knowledge:

• Programming/scripting skills such as C, Assembly, Perl, Python, etc.
• Prior lead digital design experience on large, commercially successful, mixed-signal SOCs
• Prior experience developing digital solutions with high speed serial data interfaces
• Prior experience in developing digital solutions for switching voltage regulator systems