Job overview
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A group of projects on high-speed interface development
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Design based on high-speed units, DSP algorithms development
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Experience with Matlab in terms of modeling and automatic source code generation for Zynq
Our expectations
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Higher professional education in Engineering or a related discipline
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5+ of experience developing in commercial projects
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Experience with Altera Quartus, Xilinx ASE/EDK, Vivado
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Experience with simulation packages (e.g., Modelsim)
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Verilog/VHDL development experience
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Experience with digital interfaces like SRAM/DDR3/DDR4, PCIe, JESD204B, Ethernet, UART, SPI, etc.
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General understanding and the ability to correct ready-made/third-party CORE IP (open). Integration with system buses.
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Knowing the internal architecture of the FPGA and its hardware modules.
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Generation/synthesis/processing of digital and analog signals (DAC/ADC) understanding.
Desired skills of a successful candidate
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Experience with developing on C (in terms of SDK)
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Experience with Vivado HLS
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Understanding the digital signal processing – building digital filters (DF), interference-resistant digital video transmission system, Fourier transform (FT), up and down signal transform
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Experience with building interference-resistant coders/decoders
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Understanding & experience with radio modems (modulation, demodulation, principles of building radio protocols)
Key responsibilities
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Statement of work development
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Device architecture design
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Participation in the development of structural, functional, principal schemes
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FPGA programming, testing and debugging
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Technical evaluation of project implementation