Job overview
- A group of projects on high-speed interface development
- design based on high-speed units, DSP algorithms development
- Experience with Matlab in terms of modeling and automatic source code generation for Zynq.
Our expectations
- Higher professional education in Engineering or a related discipline
- 5+ of experience developing in commercial projects
- Experience with Altera Quartus, Xilinx ASE/EDK, Vivado
- Experience with simulation packages (e.g., Modelsim)
- Verilog/VHDL development experience
- Experience with digital interfaces like SRAM/DDR3/DDR4, PCIe, JESD204B, Ethernet, UART, SPI, etc.
- General understanding and the ability to correct ready-made/third-party CORE IP (open). Integration with system buses.
- Knowing the internal architecture of the FPGA and its hardware modules.
- Generation/synthesis/processing of digital and analog signals (DAC/ADC) understanding.
Desired skills of a successful candidate
- Experience with developing on C (in terms of SDK)
- Experience with Vivado HLS
- Understanding the digital signal processing – building digital filters (DF), interference-resistant digital video transmission system, Fourier transform (FT), up and down signal transform
- Experience with building interference-resistant coders/decoders
- Understanding & experience with radio modems (modulation, demodulation, principles of building radio protocols)
Key responsibilities
- Statement of work development
- Device architecture design
- Participation in the development of structural, functional, principal schemes
- FPGA programming, testing and debugging
- Technical evaluation of project implementation