We are looking for SoC Design Verification Engineer to provide design verification services for multi CPU/DSP SoC.
- Testbench development – System Verilog UVM and C tests
- Integration/development of C tests/APIs and SW build flow
- Integration/development of UVM mailboxes and HW/SW communication components
- Integration of lower level UVM testbenches
- Test plan development
- Power Aware testbench development and simulations
- Seamless porting between simulation/emulation/prototyping platforms
- Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto
- Coverage collection and closure
- Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope
Qualifications
Basic Qualifications:
- Minimum of 5+ years of experience in RTL Design and Verification area of which
- Minimum of 2+ years of experience in SoC Design Verification and HW/SW verification
- Minimum of 2+ years within any of the following:
- System Verilog UVM and vertical testbench integration
- Low-level HW/SW interaction and debug
- Multi CPU and debug architectures
- Development of fully automated flows
Preferred Qualification:
- Experience with low-level SW debug – disasm, Tarmac, trace
- Experience with coresight architecture
- Experience with embedded SW low-level concepts and debug – Tarmac, ROM, RAM, linkers, elf, disasm, code sections, cache, security
- Experience with coverage merging across simulation and emulation
- Experience with Power Aware and Gate Level Netlist in Emulation
- Experience with development of fully automated flows
- Experience with Gate Level Simulations
- Python Scripting
Applicants for employment in the US must have work authorization that does not now or in the future require sponsorship of a visa for employment authorization in the United States and with Accenture.