In this position, you would be working within Accenture Products and Platforms (APP). APP operates a portfolio of product-mindset business units inside Accenture – each with a shared mission to codify industry and functional knowledge into valuable and differentiated software assets for sale to Accenture clients or as market-facing products in clients’ own offerings. APP teams overlay Pragmatic frameworks and Agile methodologies to create value and deliver excellence every day. APP products and platforms accelerate time-to-value, ensure customer satisfaction, and drive productive, long-term client engagements. APP offers unique and rewarding opportunities and software career paths within Accenture.
Job Description
We are looking for SoC Design Verification Engineer to provide design verification services for multi CPU/DSP SoC.
- Testbench development – System Verilog UVM and C tests
- Integration/development of C tests/APIs and SW build flow
- Integration/development of UVM mailboxes and HW/SW communication components
- Integration of lower level UVM testbenches
- Test plan development
- Power Aware testbench development and simulations
- Seamless porting between simulation/emulation/prototyping platforms
- Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto
- Coverage collection and closure
- Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope
Qualifications
Basic Qualifications
- Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience)
- 1 year of experience in RTL Design and Verification area of which
- 1 year of experience in SoC Design Verification and HW/SW verification
- 1 year within any of the following:
- System Verilog UVM and vertical tetsbench integration
- Low level HW/SW interaction and debug
- Multi CPU and debug architectures
- Development of fully automated flows
Preferred Qualification
- Experience with low level SW debug – disasm, Tarmac, trace
- Experience with coresight architecture
- Experience with embedded SW low level concepts and debug – Tarmac, ROM, RAM, linkers, elf, disasm, code sections, cache, security
- Experience with coverage merging across simulation and emulation
- Experience with Power Aware and Gate Level Netlist in Emulation
- Experience with development of fully automated flows
- Experience with Gate Level Simulations
- Python Scripting
Applicants for employment in the US must have work authorization that does not now or in the future require sponsorship of a visa for employment authorization in the United States and with Accenture.